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思瑞浦微电子原厂(3PEAK):上海招聘 数字验证工程师 1名 待遇20到35K
【Job Description】
Creating test plan according to design spec.
Designing and developing verification environment
Creating UVM test cases
Creating code and function coverage report.
【Job Requirement】
1. Major in EE, CS or related, Master Degree with 2+ years or Bachelor with 5+ years working experiences in ASIC design or verification.
2. Familiar with Verilog and RTL design
3. Familiar with System-Verilog and UVM verification methodology
4. Familiar with script languages(perl,tcl,sh etc.) is a plus
5. Familiar with digital signal processing knowledge is a plus
6. Good problem solving and communication skills
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