公司简介：

Xilinx Beijing R&D center is the core team for developing the Vivado High-Level Synthesis (HLS) tool. This tool transforms a C specification(C, C++, SystemC and OpenCL) into a RTL implementation that can be synthesized into a Xilinx FPGA. It improves the productivity for hardware designers by enabling them working at a higher level of abstraction while creating high-performance hardware. It also help improves system performance for software designers as they can accelerate the computation intensive parts of their algorithms on a new compilation target, the FPGA.

职位：

RtlGen

Responsibilities:

Define the architecture for the hardware design automatically generated from high level synthesis tool.

Develop software algorithms for automatically generating the hardware design in high level synthesis tool.

Requirements：

Degree of M.S or Ph.D in computer science or electrical engineering.

More than 3 years’ experience on complex hardware architecture design, e.g. pipeline, interconnect, memory controller and so on.

Strong design/implementation skills in Verilog/VHDL.

Experience on C++ programing

Good learning competency and self-motivated

Fluent English

Preferred knowledge and experience:

Experience on computer architecture or micro-architecture design.

Experience on timing optimization of digital design.

Experience on software algorithms and data structures.

Scheduling/Binding

Responsibilities:

Developing the software algorithms that is central to behavior synthesis strategy for high level synthesis tool

Requirements：

Degree of M.S or Ph.D in computer science or electrical engineering

Solid understanding on performance optimization of hardware design

Strong experience on software algorithms and data structures.

Expert on C++ programing

Good learning competency and self-motivated

Fluent English

Preferred knowledge and experience:

Experience on high-level synthesis algorithms

Experience on compiler algorithms, familiar with one of GCC/LLVM

Experience on hardware architecture design and optimization

Experience on EDA tool developments

Cosim

Responsibilities:

Develop the automatic self-verification platform for high-level synthesis tool.

Requirements：

Degree of M.S or Ph.D in computer science or electrical engineering.

Experience on VHDL/Verilog hardware description languages

Experience on simulation based hardware verification

Good trouble shooting and debugging skills to find the root cause of RTL issues

Experience with one scripting language (such as Tcl, Python, Perl)

Good learning competency and self-motivated

Fluent English

.

Preferred knowledge and experience:

Experience on software algorithms and data structures

Experience on object-oriented languages (C++) programming

Experience on OVM/VMM/AVM verification methodology

待遇：全年13薪+一年两次bonus奖金+股票奖励。福利齐全，人性化管理，工作氛围良好。工作地点在盘古，环境不错。

Xilinx公司股价最近一年内翻倍了（所有员工都持有股票奖励），而且我们team正在重构HLS工具，现在是加入的大好时机！

简历请发送至：weiw@xilinx.com.